The present invention relates to a method and apparatus for performing certain floating point arithmetic operations in a data processing system. More particularly, the invention relates to an apparatus and method for implementing the apparatus, wherein five multiples of the divisor are produced without additional registers, for use in the divide iterations to produce a quotient, and wherein the floating point division circuit has a single carry-save adder circuit.
The use of floating point arithmetic operations in a data processing system has been a common practice practically since the inception of computer technology. The development of floating point arithmetic hardware has taken many forms, usually with the objectives of simplifying the hardware construction, or enhancing the speed of the arithmetic processing operation. The four arithmetic operations of add, subtract, multiply and divide have usually been accomplished by using specialized subsets of processes involving addition and subtraction. For example, multiplication operations have in many cases been performed by repeated addition processes, and division has been accomplished by a process of repeated subtraction. The efforts made to speed up these processing operations have focused on enhancements and simplifications of hardware circuit design, particularly the adder circuit, which ultimately limits the maximum processing speed of all arithmetic operations. In the case of division, efforts have been made to increase the speed of operation by calculating partial quotients, or by simultaneously predicting multiple quotient bits, to reduce the number of addition or subtraction iterations required for the divide calculation.
An American national standard has been developed in order to provide a uniform system of rules for governing the implementation of floating point arithmetic systems. This standard is identified as ANSI/IEEE Standard No. 754-1985, and is incorporated by reference herein. In the design of floating point arithmetic systems and algorithms, it is a principal objective to achieve results which are consistent with this standard, to enable users of such systems and algorithms to achieve conformity in the calculations and solutions to problems even though the problems are solved using different computer systems. The standard specifies basic and extended floating point number formats, arithmetic operations, conversions between integer and floating point formats, conversions between different floating point formats, conversions between basic format floating point numbers and decimal strings, and the handling of certain floating point exceptions.
The typical floating point arithmetic operation may be accomplished in either single precision or double precision format. Each of these formats utilizes a sign, exponent and fraction field, where the respective fields occupy predefined portions of the floating point number. In the case of a 32-bit single precision number the sign field is a single bit occupying the most significant bit position; the exponent field is an 8-bit quantity occupying the next-most significant bit positions; the fraction field occupies the least significant 23-bit positions. In the case of a double precision floating point number the sign field is a single bit occupying the most significant bit position; the exponent field is an 11-bit field occupying the next-most significant bit positions; the fraction field is a 52-bit field occupying the least significant bit positions.
After each floating point answer is developed, it must be normalized and then rounded. When the answer is normalized, the number of leading zeros in the fraction field is counted. This number is then subtracted from the exponent and the fraction is shifted left until a "1" resides in the most significant bit position of the fraction field. Certain floating point answers cannot be normalized because the exponent is already at its lowest possible value and the most significant bit of the fraction field is not a "1".
In designing the hardware and logic for performing floating point arithmetic operations in conformance with ANSI/IEEE Standard 754-1985, it is necessary and desirable to incorporate certain additional indicator bits into the floating point hardware operations. These indicator bits are injected into the fraction field of the floating point number, and are used by the arithmetic control logic to indicate when certain conditions exist in the floating point operation. For example, an "implicit" bit I is created by the arithmetic control logic when the exponent of the floating point number has a nonzero value. The implicit bit I is created at the time a floating point number is loaded into the arithmetic registers, and the implicit bit I occupies the first bit position in the fraction field of the number. In addition, a "guard" bit G is set by the floating point control logic during certain arithmetic operations, as an indicator of the loss of precision of the floating point number being processed. The G bit is set when a right shift, required for normalization, shifts a significant bit off the right side of the register capacity. For single precision numbers the G bit occupies bit position 25 in the fraction field; for double precision numbers the G bit occupies position 54 in the fraction field. A "round" bit R is similarly used for certain floating point arithmetic operations, and is set by the arithmetic control logic, and the R bit occupies bit position 26 in the fraction field of a single precision number, and bit position 55 in the fraction field of a double precision number. Finally, a "sticky" bit S is an indicator bit which is set in certain floating point arithmetic operations when any lower precision bit is a "1", as an indicator that the floating point number has lost some precision. The S bit occupies position 27 of the fraction field in a single precision floating point number, and position 56 in the fraction field of a double precision floating point number.
The three extra bits in the fraction field are used exclusively for rounding operations, after the result has been normalized. The guard (G) and round (R) bits are treated as if they are a part of the fraction; they are shifted with the rest of the fraction, and included in all arithmetic. The sticky (S) bit is not shifted with the fraction, but is included in the arithmetic. It acts as a "catcher" for 1's shifted off the right of the fraction; when a 1 is shifted off the right side of the fraction, the S bit will remain a 1 until normalization and rounding are finished.
In a rounding operation there are typically four modes of rounding which are used, as follows:
(1) round to nearest;
(2) round to positive infinity;
(3) round to negative infinity;
(4) round to zero.
The "round to nearest" mode means that the value nearest to the infinitely precise result should be delivered. If the two nearest representable values are equally near, the one with its least significant bit zero shall be delivered. The "round to positive infinity" mode means that the value closest to and not less than the infinitely precise result should be delivered. The "round to negative infinity" mode means that the value closest to and not greater than the infinitely precise result should be delivered. The "round to zero" mode means that the result delivered should be the closest to but not greater in magnitude than the infinitely precise result. If none of the G, R, and S bits are a "1", no rounding will be accomplished regardless of the mode of rounding selected.
Unfortunately, any arithmetic circuit utilizing an adder for carrying out an addition or subtraction inevitably involves the generation of carry bits which are propagated from least significant bit positions to more significant bit positions, and can in fact be propagated throughout all bit positions during an arithmetic operation. This has the affect of extending the processing time required for completing a calculation, and various design efforts have been made to deal with this problem. For example, U.S. Pat. No. 4,754,422, issued June 28, 1988, discloses a dividing apparatus utilizing three carry-save adders in an effort to produce a plurality of quotient bits during each iteration or cycle of arithmetic operation. U.S. Pat. No. 3,621,218, issued Nov. 16, 1971, discloses a high-speed divider utilizing a single carry-save adder for producing a plurality of quotient bits during each iteration of the arithmetic operation, and a plurality of registers for holding a sequence of partial quotients used in the operation.
IBM Technical Disclosure Bulletin, Volume 14, No. 11, Apr. 1972 (pages 3279-3281) discloses a divider for producing two quotient bits per iteration, utilizing two carry-save adders and certain multiples of the divisor to speed up the operation.
The present invention is an improvement over the foregoing disclosures, for generating two quotient bits per iteration by producing five multiples of the divisor, with the improved feature of using only a single carry-save adder, and no additional registers for holding the divisor multiples. It is therefore a principal object of this invention to provide a floating point divide circuit, and method for operating the circuit, which generates two quotient bits per iteration by producing five multiples of the divisor without requiring additional registers, and utilizes only a single carry-save adder.
It is a further object of the present invention to provide a floating point division circuit capable of generating two quotient bits per iteration, by utilizing a circuit common to other floating point arithmetic operations such as add, subtract and multiply.
It is a further object of the present invention to provide an apparatus and method for floating point arithmetic operations, wholly in conformance with ANSI/IEEE Standard No. 754-1985.
It is a further object of the present invention to provide an apparatus and method for achieving certain floating point arithmetic operations in a shorter time period than previously obtained, through the selective reduction in the number of machine cycles required to provide these operations.